Stanford Ultra Low Power CMOS

Stanford has been developing a low voltage CMOS technology which could have a signiicant impact on a wide range of products from personal digital assistants to volume silicon supercomputers. The technology achieves a unique combination of high performance and low energy per operation by combining aggressive voltage scaling with process optimization. The approach is based on the insight that the overall energy in the system can be minimized by balancing the leakage and switching energy. This permits much lower threshold voltages than are normally designed into standard processes, and permits short channel devices to operate at much lower supply voltages without loss of performance. The approach electrically adjusts the threshold voltage depending on circuit activity and to compensate for process variations. This talk describes the approach and gives some experimental results we have obtained from chips fabricated at Stanford's Center for Integrated Systems.